The present invention generally relates to a method for forming a liner for a conductor in an electronic structure and device formed and more particularly, relates to a method for forming an open-bottom liner for a via plug in a semiconductor structure and device formed by the method.
In modern semiconductor devices, the interconnect wiring structures consist of multiple levels of metal lines (wires) and dielectric layers (insulator). The lines may take the form of etched films on the dielectric surface, or embedded metal wires fabricated in trenches in the dielectric. This latter fabrication technique is known as Damascene processing. A via is a vertical connection, usually circular or square in cross-section, which electrically connects wires on different dielectric levels. If a via is formed in conjunction with a Damascene (embedded) line, the fabrication process is known as xe2x80x9cdual Damascenexe2x80x9d. A schematic view of a dual damascene structure 10 incorporating such wiring structures is shown in FIG. 1. The structure 10 consists of two layers of inter-level dielectric materials 12,14, into which features containing a conductive metal 16,18 such as Cu or Al are provided. An adhesion diffusion barrier liner 20 is used to line the openings to separate the conductive metal 16,18 from the dielectric matrix 12,14. A capping layer 22 is further used to complete the encapsulation of the conductors 16,18. A suitable capping layer 22 is normally formed of silicon nitride. The layers are formed as shown in FIG. 1 to provide electrical connection to the underlying circuit element 24. The adhesion diffusion barrier layer 20, or the liner layer, is an important element for the successful operation of the semiconductor structure 10. It is frequently formed of a material, or materials that are impermeable to the materials that form the conductors 16,18. Its function is to provide adhesion and prevent the diffusion of the conductor materials 16,18 into the dielectric matrix material 12,14 which would lead to electrical and structural problems.
In the conventional structure 10 shown in FIG. 1, the very property that leads to its utilization as a liner, i.e. its impermeability towards the conductor material, leads to a phenomenon of electromigration-induced voiding. The phenomenon is shown in FIG. 2. Electrons flow continuously from the circuit element 24 through the conductor material 16 and the boundary layer 26 to the upper conductor 18. The boundary layer 26 is part of the liner 20 formed at the bottom of the upper conductor 18. When a voltage is applied, the electron current will be constant across the boundary layer 26 as dictated by the Kirchoff""s Law. An electromigration process thus occurs through the boundary layer 26 in which atoms of the conductor material 18 are swept along with the electrical currents. The atoms of the lower conductor material 16 are accumulated below the boundary layer 26. On the upper side of the boundary layer 26, there is the same electrical current such that atoms of the upper conductor 18 move in the same direction as atoms in the lower conductor 16 in an upward direction. At the boundary layer 26, however, neither the movement of atoms of the liner layer 22, nor the atoms 16 through the liner layer 22, can occur. The material chosen for the liner layer 22 is very low diffusivity and prevents the permeation of the atoms of the conductor material 16. Thus, at the top of the boundary layer 26, electromigration driving force pushes the diffusing atoms of the conductor 18 away from the boundary layer 26, while atoms from the conductor 16 from below the boundary layer 26 cannot flow through the boundary layer 26 to take their place. This is known in semiconductor technology as flux divergence. The result is the formation of an electromigration-induced void 30, shown in FIG. 2. The formation of the void 30 dramatically increases the resistance of the conductor 18 and thus leads to the formation of an open circuit. Even though materials chosen for the conductors are frequently optimized for resistance to electromigration, the electromigration phenomenon can never be entirely eliminated and thus, the failure mechanism caused by electromigration-induced voids is always a reliability issue.
A widely used method for liner formation in the semiconductor industry is sputter deposition, a physical vapor deposition (PVD) technique. Sputter deposition occurs by the flow of metal atoms at low vapor pressure toward a target. It is also known as a line-of-sight deposition process. Sputtered atoms tend to have a near-unity sticking coefficient, i.e. they tend to stick and deposit on the first surface they encounter. Sputter deposition can be carried out in the semiconductor industry by a variety of techniques, i.e. conventional, collimated and ionized. In the conventional sputter process, a widely divergent flux of atoms flows to a surface and thus tend to deposit atoms on planar surfaces and at the very top corners of high aspect ratio features. The collimated sputtering technique utilizes a geometrical filter, thus resulting in a mostly normal incidence flux of atoms to a surface. This leads to a deposition in which the planar surface receives a thick deposit, the sidewalls of a feature receive a thin deposit, while the bottom surface of the feature receives an intermediate amount of deposit.
The third sputtering technique, i.e. the ionized sputter deposition relies on the in-flight ionization of the metal atoms, such that a majority of the atoms are deposited on the surface as ions. The ionized sputter deposition therefore results in an intrinsically normal incidence deposition, and the ability to control the kinetic energy of the depositing species by adjusting the sample bias voltage. This latter feature is important for self-sputtering of the deposited film. When the sample bias voltage is sufficiently negative (relative to the plasma potential), the depositing metal ions can cause physical sputtering of the already-deposited metal particles. In the case of a trench or via, this can lead to a reduction in the deposition on the bottom surface where the ions impact, resulting in redeposition of those atoms on the sidewalls. This redeposition process can be a very desirable process for altering the sidewall thickness. However, too much resputtering can result in the complete removal of the deposited films in both the bottom of a via as well as the bottom of a trench. The latter feature is undesirable and should be avoided.
Another processing technique that is used for depositing a liner structure is chemical vapor deposition (CVD). The CVD technique is not a line-of-sight process since it relies on a sequence of steps, i.e. the gas phase condensation of the precursors, the reaction steps, and the emission of a volatile product molecules. The CVD deposition technique can be optimized to result in mostly conformal films, similar to those shown in FIG. 1. The CVD technique provides improved step coverage of the deposited film at any point in the feature as compared to the thickness on the top or planar areas. However, the CVD method as currently practiced in the semiconductor industry, would not result in the deposition of a liner structure that is open-bottomed.
It is therefore an object of the present invention to provide a method for forming a liner structure for a conductor in a semiconductor structure that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for forming an open-bottom liner for a conductor in a semiconductor structure for improved electrical conductance with an underlying conductive layer.
It is a further object of the present invention to provide a method for forming an open-bottom liner for a conductor in a semiconductor structure by a modified chemical vapor deposition technique.
It is another further object of the present invention to provide a method for forming an open-bottom liner for a via plug in a semiconductor structure in a cold-wall low pressure chemical vapor deposition chamber.
It is still another object of the present invention to provide a method for forming an open-bottom liner for a via plug in a semiconductor structure by heating a semiconductor substrate to a temperature of at least 350xc2x0 C., and flowing a precursor gas into the chamber at a partial pressure of not higher than 10 mTorr.
It is yet another object of the present invention to provide a method for forming an open-bottom liner for a via plug in a semiconductor structure wherein an open-bottom tungsten liner is formed for a copper via plug.
It is still another further object of the present invention to provide an electronic structure that has a metal conductor formed therein wherein a metal liner layer covers sidewalls of the metal conductor while leaving a bottom of the conductor uncovered.
It is yet another further object of the present invention to provide an electronic structure that has a metal conductor formed therein wherein a tungsten layer covers sidewalls of the copper via while the bottom of the copper via plug is substantially uncovered.
In accordance with the present invention, a method for forming an open-bottom liner for a conductor in an electronic structure and a device formed by the method are disclosed.
In a preferred embodiment, a method for forming an open-bottom liner for a conductor in an electronic structure can be carried out by the operating steps of first providing a pre-processed electronic substrate that has a dielectric layer on top, forming via openings in the dielectric layer by exposing an underlying conductive layer, positioning the electronic substrate in a chemical vapor deposition chamber, heating the electronic substrate to a temperature of at least 350xc2x0 C., flowing a precursor gas, either neat or by means of a carrier gas, into the CVD chamber to a deposition partial pressure not higher than 10 mTorr, and depositing metal from the precursor gas onto sidewalls of the via openings while leaving bottoms of the via openings substantially uncovered.
The method for forming an open-bottom liner for a conductor in an electronic substrate may further include the step of providing a pre-processed silicon wafer that has a dielectric material, such as polyimide, silicon nitride, or silicon oxide layer on top. The method may further include the step of heating the electronic substrate to 400xc2x0 C. prior to the deposition step, or the step of flowing W(CO)6 into the CVD chamber either neat or by means of a carrier gas for depositing W into the via openings and forming a liner on the sidewalls. The method may further include the step of re-sputtering W to a thickness of less than 5 nm on the sidewalls by simultaneously removing residual W deposited at a bottom of the via openings by the re-sputtered W ions. The method may further include the step of depositing a Cu seed layer on top of the W liner in the via openings, or the step of depositing a Cu seed layer on top of the W layer by an ionized physical vapor deposition technique at a kinetic energy of the Cu atoms of at least 50 eV, or the step of depositing a Cu seed layer on top of the W layer to a sufficient thickness such that a bond strength achieved between a subsequently deposited Cu film and the W liner is at least 0.4 MPamxc2xd.
The present invention is further directed to the method for forming via plugs in a semiconductor substrate that can be carried out by the steps of providing a semiconductor substrate that has a dielectric layer deposited on top, forming via openings in the dielectric layer exposing an underlying conductive layer, positioning the semiconductor substrate in a CVD chamber, heating the semiconductor substrate to a temperature of at least 350xc2x0 C., flowing a precursor gas into the CVD chamber to a deposition partial pressure not higher than 10 mTorr, depositing a metal liner layer from the precursor gas onto sidewalls in the via openings without depositing a substantial amount on the bottoms of the via openings, depositing a metal seed layer into the via openings covering sidewalls and bottoms of the via openings, and depositing a metal film of the same material as the metal seed layer filling the via openings and establishing electrical contact with the underlying conductive layer.
The method for forming via plugs in a semiconductor substrate may further include the step of depositing a metal liner layer in W and depositing a metal seed layer in Cu. The present invention is still directed to an electronic structure that has a metal conductor covered on its sidewalls by a liner layer formed therein which includes an electronic substrate that has a dielectric layer formed on top of a conductive layer, a via opening formed in the dielectric layer exposing the conductive layer, a metal liner covers sidewalls of the via opening while substantially leaving a bottom of the via opening uncovered, and a conductive metal filling the via opening in electrical contact with the conductive layer forming the metal conductor.
In the electronic structure that has a metal conductor therein covered on its sidewalls by a liner layer, the metal liner includes W and the conductive layer includes Cu. The electronic structure further includes a metal seed layer deposited inbetween the metal liner layer and the metal conductor. The metal seed layer may be formed of Cu.